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M39P0R9080E4 M39P0R1080E4
512 Mb or 1 Gb (x16, multiple bank, multilevel, burst) Flash memory 256 Mbit low power SDRAM, 1.8 V supply, multichip package
Features
Multichip package - 1 die of 512 Mbit (32 Mb x16) or 1 Gbit (64 Mb x16) multiple bank, multilevel, burst) Flash memory - 1 die of 256 Mbit (4 banks of 4 Mb x16) low power synchronous dynamic RAM Supply voltage - VDDF = VCCP = VDDQ = 1.7 to 1.95 V - VPPF = 9 V for fast program Electronic signature - Manufacturer code: 20h - 512 Mbit device code: 8819 - 1 Gbit device code: 880F ECOPACK(R) packages available
FBGA
TFBGA165 (ZAS) 9 x 11 mm
Block locking - All blocks locked at power-up - Any combination of blocks can be locked with zero latency - WPF for block lock-down - Absolute write protection with VPPF = VSS Security - 64-bit unique device number - 2112-bit user programmable OTP cells CFI (Common Flash Interface)
Flash memory
Synchronous/asynchronous read - Synchronous Burst Read mode: 108 MHz, 66 MHz - Asynchronous Page Read mode - Random access: 96 ns Programming time - 4.2 s typical word program time using Buffer Enhanced Factory Program command Memory organization - Multiple bank memory array: 64 Mbit banks (512 Mb devices) 128 Mbit banks (1Gb devices) - Four EFA (extended flash array) blocks of 64 Kbits Dual operations - program/erase in one bank while read in others - No delay between read and write operations 100,000 program/erase cycles per block
LPSDRAM
256 Mbit synchronous dynamic RAM - Organized as 4 banks of 4 Mwords, each 16 bits wide Synchronous burst read and write - Fixed burst lengths: 1, 2, 4, 8 words or full page - Burst types: sequential and interleaved - Clock frequency: 133 MHz (7.5 ns speed) - CAS latency 3 at 133 MHz Automatic and controlled precharge Low power features: - PASR (partial array self refresh), - TCSR (automatic temperature compensated self refresh) - DS (driver strength) - Deep Power-Down mode Auto refresh and self refresh
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www.numonyx.com 1

November 2007
Rev 2
M39P0R9080E4, M39P0R1080E4
Contents
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 A bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.1.9 2.1.10 2.1.11 2.1.12 2.1.13 2.1.14 2.1.15 Flash memory address inputs (A-A0-A-Amax) . . . . . . . . . . . . . . . . . . . . 9 Flash memory data Inputs/Outputs (A-DQ0-A-DQ15) . . . . . . . . . . . . . . . 9 Flash memory Chip Enable input (A-E) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash memory Output Enable (A-G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash memory Write Enable (A-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash memory Write Protect input (A-WP) . . . . . . . . . . . . . . . . . . . . . . . 9 Flash memory Reset (A-RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash memory Deep Power-Down (A-DPD) . . . . . . . . . . . . . . . . . . . . . 10 Flash memory Latch Enable (A-L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash memory Clock (A-K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash memory Wait (A-WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash memory A-VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash memory A-VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory A-VPP program supply voltage . . . . . . . . . . . . . . . . . . . . 11 Flash memory A-VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LPSDRAM address Inputs (B-A0-B-A12) . . . . . . . . . . . . . . . . . . . . . . . 11 LPSDRAM Bank Select Address Inputs (B-BA0-B-BA1) . . . . . . . . . . . . 11 LPSDRAM Data Inputs/Outputs (B-DQ0-B-DQ15) . . . . . . . . . . . . . . . . 12 LPSDRAM Chip Select (B-E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Column Address Strobe (B-CAS) . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Row Address Strobe (B-RAS) . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Write Enable (B-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Clock Input (B-K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Clock Enable (B-KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Lower/Upper Data Input/Output Mask (B-LDQM/B-UDQM) 12 LPSDRAM B-VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM B-VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LPSDRAM B-VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2
B bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13
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Contents
M39P0R9080E4, M39P0R1080E4
3 4 5 6 7 8
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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M39P0R9080E4, M39P0R1080E4
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TFBGA165 9 x 11 mm - 12 x 15 ball array, 0.65 mm pitch, package mechanical data . . . 20 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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List of figures
M39P0R9080E4, M39P0R1080E4
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional block diagram - A bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional block diagram - B bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TFBGA165 9 x 11 mm - 12 x 15 ball array, 0.65 mm pitch, package outline . . . . . . . . . . . 19
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M39P0R9080E4, M39P0R1080E4
Description
1
Description
The M39P0R9080E4 and M39P0R1080E4 combine two memory devices in a multichip package:

a 512-Mbit (M58PR512LE) or 1 Gbit (M58PR001LE) multiple bank Flash memory a 256-Mbit low power synchronous DRAM (the M65KA256Ax)
The purpose of this document is to describe how the two memory components operate with respect to each other. It should be read in conjunction with the M58PRxxxLE and M65KA256Ax datasheets, which fully detail all the specifications required to operate the Flash memory and LPSDRAM components. The memory is offered in a stacked TFBGA165 package, and is supplied with all the bits erased (set to `1'). Figure 1. Logic diagram
A-VDD A-VPP A-VDDQ B-VDDQ
B-VDD
A-A0-A-Amax B-A0-B-A12 B-BA0-B-BA1 A-E A-G A-W A-RP A-WP A-L A-K A-DPD B-E B-RAS B-CAS B-K B-KE B-W M39P0R09080E4 M39P0R01080E4 13 2
16 A-DQ0-A-DQ15
16
B-DQ0-B-DQ15
A-WAIT B-UDQM B-LDQM
B-VSS
A-VSS
AI13469
1. The Flash memory component is connected to the A bus whereas the LPSDRAM component is on the B bus. 2. Amax is A-A24 in the M39P0R9080E4 and it is A-A25 in the M39P0R1080E4.
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Description Table 1. Signal names
Function Not connected internally Do not use as internally connected
M39P0R9080E4, M39P0R1080E4
Signal NC DU
Direction N/A N/A
Flash memory signals A-A0-A-Amax(1) A-DQ0-A-DQ15 A-E A-G A-W A-RP A-WP A-L A-K A-WAIT A-DPD A-VDDQ A-VPP A-VDD A-VSS Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Reset Write Protect Latch Enable Burst Clock Wait Deep Power-Down Power supply for I/O buffers Optional supply voltage for fast program and erase Power supply Ground Input Input/output Input Input Input Input Input Input Input Output Input Power supply Power supply Power supply N/A
Low Power SDRAM signal B-A0-B-A12 B-DQ0-B-DQ15 B-E B-W B-K B-KE B-CAS B-RAS B-BA0, B-BA1 B-UDQM B-LDQM Address Inputs Data Inputs/Outputs Chip Enable Write Enable LPSDRAM Clock LPSDRAM Clock Enable Column Address Strobe Row Address Strobe Bank Select Upper Data Input/Output Mask Lower Data Input/Output Mask Power supply Input/output supply voltage Ground Input Input/output Input Input Input Input Input Input Input Input/output Input/output Power supply Power supply N/A
B-VDD
B-VDDQ B-VSS
1. Amax is A24 in the M39P0R9080E4 and it is A25 in the M39P0R1080E4.
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M39P0R9080E4, M39P0R1080E4 Figure 2.
1
Description
TFBGA connections (top view through package)
2 3 4 5 6 7 8 9 10 11 12
A
DU
B-A2
B-A0
B-BA0
B-A11
B-A12
B-A8
B-A6
B-A4
DU
B
DU
A-A15
B-A3
B-A1
B-BA1
B-W
NC
B-A9
B-A7
B-A5
NC
DU
C
A-A13
A-A14
A-A16
A-VSS
NC
NC
B-KE
NC
A-VSS
NC
A-DQ7
A-DQ14
D
A-A12
A-A22
NC
B-A10
B-VDD
B-E
NC
NC
B-K
A-VSS
A-DQ15
A-DQ6
E
A-A11
A-A21
NC
A-DPD
NC
B-RAS
B-CAS
NC
A-WAIT
A-VDDQ
NC
A-DQ13
F
A-A10
A-A20
A-W
A-VSS
NC
A-VSS
A-VDDQ
A-VSS
A-DQ5
G
A-A9
NC
A-WP
NC
NC
B-VDD
NC
A-L
A-DQ12
DQ4
H
A-A8
A-A24
A-A25
A-VSS
A-E
A-VDD
A-VSS
NC
NC
A-K
J
A-A18
A-A19
A-A23
NC
NC
NC
NC
A-G
A-DQ10
A-DQ11
K
A-A7
A-A17
NC
A-VSS
B-VDD
NC
A-VSS
A-VDDQ
A-VSS
A-DQ3
L
A-A5
A-A6
NC
NC
A-VDD
NC
NC
A-VPP
A-RP
A-VDDQ
NC
A-DQ2
M
A-A3
A-A4
NC
B-VDDQ
B-LDQM
B-VDDQ
B-VDDQ
B-UDQM
B-VDDQ
A-VSS
A-DQ1
A-DQ9
N
A-A1
A-A2
B-VSS
NC
B-VSS
A-VSS
B-VSS
NC
B-VSS
NC
A-DQ8
A-DQ0
P
DU
A-A0
B-DQ1
B-DQ3
B-DQ5
B-DQ7
B-DQ8
B-DQ10
B-DQ12
B-DQ14
NC
DU
R
DU
B-DQ0
B-DQ2
B-DQ4
B-DQ6
B-DQ9
B-DQ11
B-DQ13
B-DQ15
DU
AI13470
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Signal descriptions
M39P0R9080E4, M39P0R1080E4
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1
A bus
All Flash memory signals are connected to the A bus. They are described below.
2.1.1
Flash memory address inputs (A-A0-A-Amax)
Amax is the highest order Address Input. It is equal to A-A24 in the M39P0R9080E4, and to A-A25 in the M39P0R1080E4. The Address Inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the Command Interface of the Program/Erase Controller.
2.1.2
Flash memory data Inputs/Outputs (A-DQ0-A-DQ15)
The Data I/O output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation.
2.1.3
Flash memory Chip Enable input (A-E)
The Chip Enable input activates the memory control logic, input buffers, decoders, and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance, and the power consumption is reduced to the standby level.
2.1.4
Flash memory Output Enable (A-G)
The Output Enable input controls data outputs during the bus read operation of the memory.
2.1.5
Flash memory Write Enable (A-W)
The Write Enable input controls the bus write operation of the Flash memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable, whichever occurs first.
2.1.6
Flash memory Write Protect input (A-WP)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the lock-down is enabled and the protection status of the lockeddown blocks cannot be changed. When Write Protect is at VIH, the lock-down is disabled and the locked-down blocks can be locked or unlocked. (See the M58PRxxxLE datasheet for details).
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M39P0R9080E4, M39P0R1080E4
Signal descriptions
2.1.7
Flash memory Reset (A-RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to the M58PRxxxLE datasheet, for the value of IDD2. After Reset, all blocks are in the locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode, the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to the M58PRxxxLE datasheet).
2.1.8
Flash memory Deep Power-Down (A-DPD)
The Deep Power-Down input is used to put the Flash memory in deep power-down mode. When the Flash memory is in standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting the Deep Power-Down input causes the memory to enter the deep power-down mode. When the device is in the deep power-down mode, the memory cannot be modified and the data is protected. The polarity of the A-DPD pin is determined by ECR14. The Deep Power-Down input is active Low by default.
2.1.9
Flash memory Latch Enable (A-L)
The Latch Enable input latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.1.10
Flash memory Clock (A-K)
The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations.
2.1.11
Flash memory Wait (A-WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH, Output Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or one data cycle in advance.
2.1.12
Flash memory A-VDD supply voltage
A-VDD provides the power supply to the internal core of the Flash memory component. It is the main power supply for all operations (read, program and erase).
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Signal descriptions
M39P0R9080E4, M39P0R1080E4
2.1.13
Flash memory A-VDDQ supply voltage
A-VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently of A-VDD. A-VDDQ can be tied to A-VDD or can use a separate supply. A-VDDQ is sampled at the beginning of program/erase operations. If A-VDDQ is lower than VLKOQ, the device is reset.
2.1.14
Flash memory A-VPP program supply voltage
A-VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If A-VPP is kept in a low voltage range (0V to A-VDDQ) AVPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while A-VPP > VPP1 enables these functions (see the M58PRxxxLE datasheet for the relevant values). A-VPP is only sampled at the beginning of a program or erase operation; a change in its value after the operation has started does not have any effect and program or erase operations continue. If A-VPP is in the range of VPPH it acts as a power supply pin. In this condition A-VPP must be stable until the program/erase algorithm is completed.
2.1.15
Flash memory A-VSS ground
A-VSS ground is the reference for the Flash memory's core supply. It must be connected to the system ground.
Note:
Each device in a system should have A-VDD, A-VDDQ and A-VPPF decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 6: AC measurement load circuit. The PCB track widths should be sufficient to carry the required A-VPP program and erase currents.
2.2
B bus
All LPSDRAM signals are connected to the B bus. They are described below.
2.2.1
LPSDRAM address Inputs (B-A0-B-A12)
The B-A0-B-A12 Address Inputs are used to select the row or column to be made active. If a row is selected, all thirteen, B-A0-B-A12 Address Inputs are used. If a column is selected, only the nine least significant Address Inputs, B-A0-B-A8, are used. In this latter case, BA10 determines whether Auto Precharge is used. If B-A10 is High (set to `1') during read or write, the read or write operation includes an auto precharge cycle. If B-A10 is Low (set to `0') during read or write, the read or write cycle does not include an auto precharge cycle.
2.2.2
LPSDRAM Bank Select Address Inputs (B-BA0-B-BA1)
The B-BA0 and B-BA1 Banks Select Address Inputs select the bank to be made active. When selecting the addresses, the device must be enabled, the Row Address Strobe, BRAS, must be Low, VIL, the Column Address Strobe, B-CAS, and B-W must be High, VIH. The address inputs are latched on the rising edge of the clock signal, B-K.
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M39P0R9080E4, M39P0R1080E4
Signal descriptions
2.2.3
LPSDRAM Data Inputs/Outputs (B-DQ0-B-DQ15)
The Data Inputs/Outputs output the data stored at the selected address during a read operation, or are used to input the data during a write operation.
2.2.4
LPSDRAM Chip Select (B-E)
The Chip Select input B-E activates the LPSDRAM state machine, address buffers and decoders when driven Low, VIL. When High, VIH, the device is not selected.
2.2.5
LPSDRAM Column Address Strobe (B-CAS)
The Column Address Strobe, B-CAS, is used in conjunction with Address Inputs B-A8-B-A0 and B-BA1-B-BA0, to select the starting column location prior to a read or write operation.
2.2.6
LPSDRAM Row Address Strobe (B-RAS)
The Row Address Strobe, B-RAS, is used in conjunction with Address Inputs B-A11-B-A0 and B-BA1-B-BA0, to select the starting address location prior to a read or write.
2.2.7
LPSDRAM Write Enable (B-W)
The Write Enable input, B-W, controls writing to the LPSDRAM.
2.2.8
LPSDRAM Clock Input (B-K)
The Clock signal, B-K, is used to clock the read and write cycles. During normal operation, the Clock Enable pin, B-KE, is High, VIH. The clock signal B-K can be suspended to switch the device to the self refresh, power-down or deep power-down mode by driving B-KE Low, VIL.
2.2.9
LPSDRAM Clock Enable (B-KE)
The Clock Enable, B-KE, pin is used to control the synchronizing of the signals to Clock signal B-K. The signals are clocked when B-KE is High, VIH When B-KE is Low, VIL, the signals are no longer clocked and data read and write cycles are extended. B-KE is also involved in switching the device to the self refresh, power-down and deep power-down modes.
2.2.10
LPSDRAM Lower/Upper Data Input/Output Mask (B-LDQM/B-UDQM)
Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals used to mask the read or write data. The DQM latency is two clock cycles for read operations and there is no latency for write operations.
2.2.11
LPSDRAM B-VDD supply voltage
B-VDD provides the power supply to the internal core of the LPSDRAM component. It is the main power supply for all operations (read and write).
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Signal descriptions
M39P0R9080E4, M39P0R1080E4
2.2.12
LPSDRAM B-VDDQ supply voltage
B-VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently of B-VDD. B-VDDQ can be tied to B-VDD or can use a separate supply. It is recommended to power-up and power-down B-VDD and B-VDDQ together to avoid certain conditions that would result in data corruption.
2.2.13
LPSDRAM B-VSS ground
Ground, B-VSS, is the reference for the LPSDRAM's core power supply. It must be connected to the system ground.
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M39P0R9080E4, M39P0R1080E4
Functional description
3
Functional description
The M39P0R9080E4 and M39P0R1080E4 consist of two distinct buses - the A and B buses. The Flash memory component is connected to the A bus and the LPSDRAM component is connected to the B bus. The connections are shown in Figure 3 and Figure 4. The components, therefore, have separate signals, separate power supplies, and grounds and can be operated simultaneously with no risk of bus contention. Figure 3. Functional block diagram - A bus
A-VDD A-VDDQ A-VPP 16 A0-Amax A-W A-E A-G A-RP A-WP A-L A-K A-DPD 512 Mbit or 1 Gbit Flash memory A-WAIT DQ0-DQ15
A-VSS
AI13471
14/23
Functional description Figure 4. Functional block diagram - B bus
B-VDD B-VDDQ
M39P0R9080E4, M39P0R1080E4
13 B-A0-B-A12 2 BA0-BA1 B-E B-RAS B-CAS B-K B-KE B-W 256 Mbit LPSDRAM B-UDQM B-LDQM 16 B-DQ0-B-DQ15
B-VSS
AI13472
Main bus operations
AS the Flash memory and LPSDRAM components are connected to separate buses, there is no limitation to the modes allowed in one of them while the other is active. Refer to the M58PRxxxLE and M65KA256Ax datasheets for the details of the each memory's bus operations.
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M39P0R9080E4, M39P0R1080E4
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer to the Numonyx SURE Program and other relevant quality documents. Table 2.
Symbol TA TBIAS TSTG VIO VDDF VDDS VDDQ VPPF IO tVPPH
Absolute maximum ratings
Value Parameter Min Ambient operating temperature Temperature under bias Storage temperature Input or output voltage Supply voltage LPSDRAM supply voltage Input/output supply voltage Program voltage Output short circuit current Time for VPP at VPPH -25 -25 -55 -0.5 -1.0 -0.5 -0.5 -1.0 Max 85 85 125 2.6 3.0 2.6 2.6 11.5 100 100 C C C V V V V V mA hours Unit
16/23
DC and AC parameters
M39P0R9080E4, M39P0R1080E4
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 3: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 3. Operating and AC measurement conditions
Parameter(1)(2) VDDF supply voltage VDDS supply voltage VDDQ supply voltage VPPF supply voltage (factory environment) VPPF supply voltage (application environment) Ambient operating temperature Impedance output (Z0) Load capacitance (CL) Output circuit protection resistance (R) Input rise and fall times Input pulse voltages Input and output timing ref. voltages
1. All voltages are referenced to VSS = 0V. 2. TA = 25C, f = 1MHz
Flash memory Min 1.7 - 1.7 8.5 -0.9 -25 Max 1.95 - 1.95 9.5 2.0 85 50 30 50 3 0 to VDDQ VDDQ/2
LPSDRAM Unit Min - 1.7 1.7 - - -25 Max - 1.95 1.95 - - 85 V V V V V C 30 pF 0.5 0.2 to 1.6 0.9 ns V V
Figure 5.
AC measurement I/O waveform
VDDQ VDDQ/2 0V
AI06161
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M39P0R9080E4, M39P0R1080E4 Figure 6. AC measurement load circuit
VCCQ/2
DC and AC parameters
R DEVICE UNDER TEST
OUT Z0 CL
AI06162a
Table 4.
Symbol CIN COUT
Capacitance
Parameter Input capacitance Output capacitance Test condition VIN = 0V VOUT = 0V Min - - Max 12 15 Unit pF pF
1. Sampled only, not 100% tested.
Please refer to the M58PRxxxLE and M65KA256Ax datasheets for further DC and AC characteristic values and illustrations.
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Package mechanical
M39P0R9080E4, M39P0R1080E4
6
Package mechanical
To meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. These packages have a lead-free, second-level interconnect. In compliance with JEDEC Standard JESD97, the category of second-level interconnect is marked on the package and on the inner box label. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 7. TFBGA165 9 x 11 mm - 12 x 15 ball array, 0.65 mm pitch, package outline
D D1
b
E
E1 ddd
BALL "B1"
e
FE A
FD
SD
e A2
A1
TFBGA-DX
1. Drawing is not to scale.
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M39P0R9080E4, M39P0R1080E4 Table 5.
Package mechanical
TFBGA165 9 x 11 mm - 12 x 15 ball array, 0.65 mm pitch, package mechanical data
Millimeters Inches Max 1.200 0.200 0.800 0.350 9.000 7.150 0.100 11.000 9.100 0.650 0.925 0.950 0.325 - - 10.900 11.100 0.4331 0.3583 0.0256 0.0364 0.0374 0.0128 - - 0.4291 0.300 8.900 0.400 9.100 0.0315 0.0138 0.3543 0.2815 0.0039 0.4370 0.0118 0.3504 0.0157 0.3583 0.0079 Typ Min Max 0.0472
Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD Min
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Part numbering
M39P0R9080E4, M39P0R1080E4
7
Table 6.
Example:
Part numbering
Ordering information scheme
M39 P 0 R 9 0 8 0 E 4 ZAS E
Device type M39 = Multichip package (Flash + LPSDRAM) Flash 1 architecture P = Multilevel, multiple bank, large buffer Flash 2 architecture 0 = No die Operating voltage R = VDDF = VDDS = VDDQ = 1.7 to 1.95V Flash 1 density 9 = 512 Mbits 1 = 1 Gbit Flash 2 density 0 = No die RAM 1 density 8 = 256 Mbit RAM 0 density 0 = No Die Parameter blocks location E = Even block flash memory configuration Product version 4 = 65 nm Flash technology, 96 ns speed; LPSDRAM Package ZAS = stacked TFBGA165 S stacked footprint. Option E = ECOPACK(R) package, standard packing F = ECOPACK(R) package, tape and reel packing
Note:
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx sales office nearest to you.
21/23
M39P0R9080E4, M39P0R1080E4
Revision history
8
Revision history
Table 7.
Date 28-Sep-2006 06-Oct-2006 28-Jun-2007 14-Nov-2007
Document revision history
Revision 0.1 0.2 1 2 Initial release. VDDF, VCCP and VDDQ voltage ranges extended to 1.95V. Changed all references to M65KA256AF to M65KA256Ax. Updated Figure 7, and removed standard packing option from Table 6. Applied Numonyx branding. Changes
22/23
M39P0R9080E4, M39P0R1080E4
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved.
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